package:
  name: riscv

dependencies:
  fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.1 }
  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }

sources:
  include_dirs:
    - rtl/include
  files:
    - rtl/include/apu_core_package.sv
    - rtl/include/riscv_defines.sv
    - rtl/include/riscv_tracer_defines.sv
    - rtl/register_file_test_wrap.sv
    - rtl/riscv_alu.sv
    - rtl/riscv_alu_div.sv
    - rtl/riscv_compressed_decoder.sv
    - rtl/riscv_controller.sv
    - rtl/riscv_cs_registers.sv
    - rtl/riscv_decoder.sv
    - rtl/riscv_int_controller.sv
    - rtl/riscv_ex_stage.sv
    - rtl/riscv_hwloop_controller.sv
    - rtl/riscv_hwloop_regs.sv
    - rtl/riscv_id_stage.sv
    - rtl/riscv_if_stage.sv
    - rtl/riscv_load_store_unit.sv
    - rtl/riscv_mult.sv
    - rtl/riscv_pmp.sv
    - rtl/riscv_prefetch_buffer.sv
    - rtl/riscv_prefetch_L0_buffer.sv
    - rtl/riscv_core.sv
    - rtl/riscv_apu_disp.sv
    - rtl/riscv_fetch_fifo.sv
    - rtl/riscv_L0_buffer.sv
    - target: asic
      files:
        - rtl/riscv_register_file_latch.sv
    - target: not(asic)
      files:
        - rtl/riscv_register_file.sv
    - target: rtl
      files:
        - rtl/riscv_tracer.sv
        - rtl/cv32e40p_sim_clock_gate.sv
