tech_cells_rtl:
  flags: [
    skip_synthesis,
  ]
  files: [
    cluster_clock_gating.sv,
    pulp_clock_gating.sv,
    pulp_clock_mux2.sv,
    pulp_clock_buffer.sv,
    pulp_clock_inverter.sv,
    pulp_clock_xor2.sv,
    pulp_buffer.sv,
    pulp_level_shifter_in.sv,
    pulp_level_shifter_in_clamp.sv,
    pulp_level_shifter_out.sv,
    pulp_level_shifter_out_clamp.sv,
    pulp_clock_and2.sv,
    cluster_clock_buffer.sv,
    cluster_clock_inverter.sv,
    cluster_clock_mux2.sv,
    cluster_clock_xor2.sv,
    cluster_level_shifter_in.sv,
    cluster_level_shifter_in_clamp.sv,
    cluster_level_shifter_out.sv,
    cluster_level_shifter_out_clamp.sv,
    cluster_clock_and2.sv,
    pulp_power_gating.sv,
    generic_rom.sv,
    generic_memory.sv,
    pad_functional.sv,
  ]

tech_cells_rtl_synth:
  files: [
   pulp_clock_gating_async.sv,
   pulp_sync.sv,
]


tech_cells_fpga:
  targets: [
    xilinx,
  ]
  files: [
    cluster_clock_gating_xilinx.sv,
    pulp_clock_gating_xilinx.sv,
    pulp_clock_mux2_xilinx.sv,
    pulp_clock_buffer.sv,
    pulp_clock_inverter.sv,
    pulp_clock_xor2.sv,
    pulp_buffer.sv,
    pulp_level_shifter_in.sv,
    pulp_level_shifter_in_clamp.sv,
    pulp_level_shifter_out.sv,
    pulp_level_shifter_out_clamp.sv,
    pulp_clock_and2.sv,
    cluster_clock_buffer.sv,
    cluster_clock_inverter.sv,
    cluster_clock_mux2.sv,
    cluster_clock_xor2.sv,
    cluster_level_shifter_in.sv,
    cluster_level_shifter_in_clamp.sv,
    cluster_level_shifter_out.sv,
    cluster_level_shifter_out_clamp.sv,
    cluster_clock_and2.sv,
    pulp_clock_gating_async.sv,
    pulp_power_gating.sv,
  ]
