riscv_regfile_rtl:
  targets: [
    rtl,
    tsmc55,
    gf22,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/register_file_test_wrap.sv,
    ./rtl/riscv_register_file_latch.sv,
  ]

riscv:
  vlog_opts: [
    -L fpnew_lib,
  ]
  incdirs: [
    ./rtl/include,
    ../../rtl/includes,
  ]
  files: [
    ./rtl/include/apu_core_package.sv,
    ./rtl/include/riscv_defines.sv,
    ./rtl/include/riscv_tracer_defines.sv,
    ./rtl/riscv_alu.sv,
    ./rtl/riscv_alu_div.sv,
    ./rtl/riscv_compressed_decoder.sv,
    ./rtl/riscv_controller.sv,
    ./rtl/riscv_cs_registers.sv,
    ./rtl/riscv_decoder.sv,
    ./rtl/riscv_int_controller.sv,
    ./rtl/riscv_ex_stage.sv,
    ./rtl/riscv_hwloop_controller.sv,
    ./rtl/riscv_hwloop_regs.sv,
    ./rtl/riscv_id_stage.sv,
    ./rtl/riscv_if_stage.sv,
    ./rtl/riscv_load_store_unit.sv,
    ./rtl/riscv_mult.sv,
    ./rtl/riscv_prefetch_buffer.sv,
    ./rtl/riscv_prefetch_L0_buffer.sv,
    ./rtl/riscv_core.sv,
    ./rtl/riscv_apu_disp.sv,
    ./rtl/riscv_fetch_fifo.sv,
    ./rtl/riscv_L0_buffer.sv,
    ./rtl/riscv_pmp.sv,
  ]
riscv_vip_rtl:
  targets: [
    rtl,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/riscv_tracer.sv,
    ./rtl/cv32e40p_sim_clock_gate.sv,
  ]
  flags: [
    skip_synthesis,
  ]

riscv_regfile_rtl:
  targets: [
    rtl,
    tsmc55,
    gf22,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/register_file_test_wrap.sv,
    ./rtl/riscv_register_file_latch.sv,
  ]

riscv_regfile_verilator:
  targets: [
    verilator,
  ]
  files: [
    ./rtl/riscv_register_file.sv,
  ]
riscv_regfile_fpga:
  targets: [
    xilinx,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/register_file_test_wrap.sv,
    ./rtl/riscv_register_file.sv,
  ]

tb_riscv:
  sim_tools: [
    questa
  ]
  synth_tools: [
    mentor
  ]
  targets: [
      rtl,
  ]
  flags: [
    skip_synthesis,
  ]
  incdirs: [
    tb/tb_riscv/include,
    rtl/include,
  ]
  files: [
    tb/tb_riscv/include/perturbation_defines.sv,
    tb/tb_riscv/riscv_simchecker.sv,
    tb/tb_riscv/tb_riscv_core.sv,
    tb/tb_riscv/riscv_perturbation.sv,
    tb/tb_riscv/riscv_random_interrupt_generator.sv,
    tb/tb_riscv/riscv_random_stall.sv,
  ]
