Metadata-Version: 2.1
Name: tsfpga
Version: 12.3.5
Summary: A flexible and scalable development platform for modern FPGA projects
Author: Lukas Vik
Author-email: 10241915+LukasVik@users.noreply.github.com
License: BSD 3-Clause License
Project-URL: Homepage, https://tsfpga.com
Project-URL: Documentation, https://tsfpga.com
Project-URL: Changelog, https://tsfpga.com/release_notes.html
Project-URL: Repository, https://github.com/tsfpga/tsfpga
Project-URL: Issues, https://github.com/tsfpga/tsfpga/issues
Keywords: asic,fpga,ci,simulation,test,vhdl,build-automation,eda,test-automation,rtl,verilog,xilinx,synthesis,vivado,systemverilog,implementation,vunit
Classifier: Development Status :: 5 - Production/Stable
Classifier: Intended Audience :: Developers
Classifier: Intended Audience :: Education
Classifier: Intended Audience :: Information Technology
Classifier: License :: OSI Approved :: BSD License
Classifier: Natural Language :: English
Classifier: Operating System :: MacOS :: MacOS X
Classifier: Operating System :: Microsoft :: Windows
Classifier: Operating System :: OS Independent
Classifier: Operating System :: POSIX :: Linux
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Topic :: Scientific/Engineering
Classifier: Topic :: Software Development :: Testing
Classifier: Topic :: Software Development
Requires-Python: >=3.9
Description-Content-Type: text/x-rst
Requires-Dist: GitPython
Requires-Dist: hdl-registers <6.0.0,>=5.1.0
Requires-Dist: rtoml
Requires-Dist: vunit-hdl <=4.7.0
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.. image:: https://tsfpga.com/logos/banner.png
  :alt: Project banner
  :align: center

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.. |pic_website| image:: https://tsfpga.com/badges/website.svg
  :alt: Website
  :target: https://tsfpga.com

.. |pic_repository| image:: https://tsfpga.com/badges/repository.svg
  :alt: Repository
  :target: https://github.com/tsfpga/tsfpga

.. |pic_chat| image:: https://tsfpga.com/badges/chat.svg
  :alt: Chat
  :target: https://github.com/tsfpga/tsfpga/discussions

.. |pic_pip_install| image:: https://tsfpga.com/badges/pip_install.svg
  :alt: pypi
  :target: https://pypi.org/project/tsfpga/

.. |pic_license| image:: https://tsfpga.com/badges/license.svg
  :alt: License
  :target: https://tsfpga.com/license_information.html

.. |pic_ci_status| image:: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml/badge.svg?branch=main
  :alt: CI status
  :target: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml

.. |pic_python_line_coverage| image:: https://tsfpga.com/badges/python_coverage.svg
  :alt: Python line coverage
  :target: https://tsfpga.com/python_coverage_html

|pic_website| |pic_repository| |pic_pip_install| |pic_license| |pic_chat| |pic_ci_status|
|pic_python_line_coverage|

tsfpga is a flexible and scalable development platform for modern FPGA projects.
With its Python-based build/simulation flow it is perfect for CI/CD and test-driven development.
The API is simple and easy to use
(a complete `simulation project <https://tsfpga.com/simulation.html>`__ is set up in less than
15 lines).

**See documentation on the website**: https://tsfpga.com

**Check out the source code on GitHub**: https://github.com/tsfpga/tsfpga

Key features
------------

* Source code-centric `project structure <https://tsfpga.com/module_structure.html>`__
  for scalability.
  Build projects, test configurations, constraints, IP cores, etc. are handled close to the
  source code, not in a central monolithic script.
* Automatically adds build/simulation sources if a recognized folder structure is used.
* Enables `local VUnit test configuration
  <https://tsfpga.com/simulation.html#local-configuration-of-test-cases>`__ without
  multiple ``run.py``.
* Handling of `IP cores <https://tsfpga.com/simulation.html#simulating-with-vivado-ip-cores>`__
  and `simlib <https://tsfpga.com/simulation.html#vivado-simulation-libraries>`__
  for your simulation project, with automatic re-compile when needed.
* Python-based `Vivado build system <https://tsfpga.com/fpga_build.html>`__ where many builds can
  be run in parallel.
* Tightly integrated with `hdl-registers <https://hdl-registers.com>`__.
  Register code generation is performed before each simulation and each build.
* Released under the very permissive BSD 3-Clause License.

The maintainers place high focus on quality, with everything having good unit test coverage and a
thought-out structure.
The project is mature and used in many production environments.
